Szukana fraza: [Abstract = "Simple latches in master\-slave configuration are used as memory elements rendering the method suitable for implementation in SSI or VLSI. It avoids extra delay elements often necessary in self\-clocked circuits. The simplicity of this method enables the design equations to be derived direct from the Algorithmic State Machines rather than flow tables. The method is illustrated by its application to the design of a VMEbus requester. The methodology is then extended to parallel controllers represented by Petri nets and automated using state assignment techniques already developed for synchronous parallel controllers."]

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