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<dc:title xml:lang="pl"><![CDATA[Reducing the number of LUTs for Mealy FSMs with state transformation]]></dc:title>
<dc:creator><![CDATA[Barkalov, Alexander]]></dc:creator>
<dc:creator><![CDATA[Titarenko, Larysa]]></dc:creator>
<dc:creator><![CDATA[Mielcarek, Kamil]]></dc:creator>
<dc:subject xml:lang="pl"><![CDATA[mealy FSM]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[FPGA]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[LUT]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[synthesis]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[extended state codes]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[combined state codes]]></dc:subject>
<dc:description xml:lang="pl"><![CDATA[In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSMcircuit is one of the most important characteristics used in logic synthesis.]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[In this paper, a method is proposed which aims at reducing LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks. Under certain conditions, each function for any logic level is represented by a circuit including a single LUT.]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[The proposed approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes into extended state codes).]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of FSM inputs and states.]]></dc:description>
<dc:publisher><![CDATA[Zielona Góra: Uniwersytet Zielonogórski]]></dc:publisher>
<dc:contributor><![CDATA[Korbicz, Józef (1951- ) - red.]]></dc:contributor>
<dc:contributor><![CDATA[Uciński, Dariusz - red.]]></dc:contributor>
<dc:date><![CDATA[2024]]></dc:date>
<dc:type xml:lang="pl"><![CDATA[artykuł]]></dc:type>
<dc:identifier><![CDATA[http://www.zbc.uz.zgora.pl/repozytorium/Content/86761/AMCS_2024_34_1_12.pdf]]></dc:identifier>
<dc:identifier><![CDATA[https://zbc.uz.zgora.pl/repozytorium/dlibra/publication/101662/edition/86761/content]]></dc:identifier>
<dc:identifier><![CDATA[oai:zbc.uz.zgora.pl:86761]]></dc:identifier>
<dc:source xml:lang="pl"><![CDATA[AMCS, volume 34, number 1 (2024)]]></dc:source>
<dc:source xml:lang="pl"><![CDATA[https://www.amcs.uz.zgora.pl/?action=papers&issue=131]]></dc:source>
<dc:language><![CDATA[eng]]></dc:language>
<dc:relation><![CDATA[oai:zbc.uz.zgora.pl:publication:101662]]></dc:relation>
<dc:rights xml:lang="pl"><![CDATA[Biblioteka Uniwersytetu Zielonogórskiego]]></dc:rights>
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