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		<identifier>oai:zbc.uz.zgora.pl:3780</identifier>
	    <datestamp>2023-06-23T11:21:48Z</datestamp>
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<dc:title xml:lang="pl"><![CDATA[Sprzętowa implementacja rozmytych sieci Petriego jako układów sterowania]]></dc:title>
<dc:creator><![CDATA[Hajduk, Zbigniew]]></dc:creator>
<dc:subject xml:lang="pl"><![CDATA[systemy rozmyte]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[sieci Petriego]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[informatyka]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[systemy cyfrowe]]></dc:subject>
<dc:description xml:lang="pl"><![CDATA[The main goal of the thesis was development of new, effective methodology of the fuzzy Petri net transformation, which may be treated as formal desctription of a control algorithm of some process - into the digital circuit, assembled using FPGA matrix structures, both as synchronous and asynchronous systems. In the work are discussed: fuzzy Petri nets, asynchronous (self clocked) digital sequential circuits and their implementation using Field-Programmable Gate Arrays (FPGA), and the automation of digital systems described by Petri nets, together with their implementation using Verilog hardware description language. The following problems were solved:]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[1. The method of how to transform a single place and the basic fragment of the fuzzy Petri net into the hardware module, as both synchronous, and asynchronous system was developed]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[2. A new fuzzy RS flip-flop was introduced as synchronous, and a synchronous circuit, which has been used for the fuzzy Petri net implementation]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[3. The method of the fuzzy Petri net synthesis which uses functional description in the Verilog language was developed]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[4. The cost of the introduced net implementation was estimated]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[5. The testing method of the hardware fuzzy Petri net was worked out, and microprocessor based testing device as a hardware and software was made]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[6. A simple description format (specification) of the fuzzy Petri net structure was described, which is suitable for engineering applications]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[7. A transformation process from textual description of the fuzzy Petri net into the complete Verilog code (as Intellectual Property Core), which describes the net behavior was automated (the computer program)]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[8. The proposed methodology of synthesis was practically verified by assembling two control devices for laboratory plants]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[promotor: dr hab. inż. Jacek Kluska, prof. Politechniki Rzeszowskiej, Politechnika Rzeszowska, Wydział Elektrotechniki i Informatyki, Katedra Informatyki i Automatyki]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[recenzenci: prof. dr. hab. inż. Marian Adamski, Uniwersytet Zielonogórski, Wydział Elektrotechniki, Informatyki i Telekomunikacji, Instytut Informatyki i Elektroniki, prof. dr hab. inż. Leszek Rutkowski, Politechnika Częstochowska, Wydział Inżynierii Mechanicznej i Informatyki, Katedra Inżynierii Komputerowej]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[Uniwersytet Zielonogórski]]></dc:description>
<dc:date><![CDATA[2006]]></dc:date>
<dc:type xml:lang="pl"><![CDATA[rozprawa doktorska]]></dc:type>
<dc:type xml:lang="pl"><![CDATA[książka]]></dc:type>
<dc:format xml:lang="pl"><![CDATA[text/html]]></dc:format>
<dc:format xml:lang="pl"><![CDATA[image/x.djvu]]></dc:format>
<dc:identifier><![CDATA[https://zbc.uz.zgora.pl/repozytorium/dlibra/publication/3337/edition/3780/content]]></dc:identifier>
<dc:identifier><![CDATA[oai:zbc.uz.zgora.pl:3780]]></dc:identifier>
<dc:language><![CDATA[pol]]></dc:language>
<dc:relation><![CDATA[oai:zbc.uz.zgora.pl:publication:3337]]></dc:relation>
<dc:rights xml:lang="pl"><![CDATA[Biblioteka Uniwersytetu Zielonogórskiego]]></dc:rights>
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