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		<identifier>oai:zbc.uz.zgora.pl:14528</identifier>
	    <datestamp>2023-06-23T11:21:17Z</datestamp>
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<dc:title xml:lang="pl"><![CDATA[Synthesis of finite state machines for programmable devices based on multi-level implementation]]></dc:title>
<dc:creator><![CDATA[Bukowiec, Arkadiusz]]></dc:creator>
<dc:subject xml:lang="pl"><![CDATA[jednostka sterująca]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[FPGA]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[dekompozycja blokowa]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[skończony automat stanów]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[synteza strukturalna]]></dc:subject>
<dc:subject xml:lang="pl"><![CDATA[układ reprogramowalny]]></dc:subject>
<dc:description xml:lang="pl"><![CDATA[New architectures of FPGA devices combine different type of logic elements like look-up tables, flip-flops and memory blocks. But standard synthesis methods utilize only look-up tables and flip-flops and it makes that device utilization is not optimal one.]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[Methods of synthesis and implementation of Mealy finite state machines into Field Programmable Devices there are presented in this work. Proposed methods of synthesis are dedicated into developed multi-level structures of digital circuits of finite state machines. Architectures of designed structures are based on existence of decoders as second-level circuits. Methods of synthesis are based on the multiple encoding. There is also proposed hardware implementation into an FPGA device of developed multi-level structures. The hardware implementation is based on an implementation with use of look-up tables and memory blocks together. It leads to better utilization of a device that standard methods gives.]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[Proposed methods have been implemented by academic software for logic synthesis of automata. Conducted experiments shown that these methods are effective for FPGA devices.]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[promotor: prof. dr hab. inż. Alexander Barkalov]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[recenzenci: prof. dr. hab. inż. Marian Adamski, prof. dr hab. inż. Tadeusz Łuba]]></dc:description>
<dc:description xml:lang="pl"><![CDATA[Uniwersytet Zielonogórski]]></dc:description>
<dc:date><![CDATA[2008]]></dc:date>
<dc:type xml:lang="pl"><![CDATA[rozprawa doktorska]]></dc:type>
<dc:format xml:lang="pl"><![CDATA[text/html]]></dc:format>
<dc:identifier><![CDATA[http://www.zbc.uz.zgora.pl/repozytorium/Content/14528/HTML/PhD-ABukowiec.pdf]]></dc:identifier>
<dc:identifier><![CDATA[https://zbc.uz.zgora.pl/repozytorium/dlibra/publication/16519/edition/14528/content]]></dc:identifier>
<dc:identifier><![CDATA[oai:zbc.uz.zgora.pl:14528]]></dc:identifier>
<dc:language><![CDATA[eng]]></dc:language>
<dc:relation><![CDATA[oai:zbc.uz.zgora.pl:publication:16519]]></dc:relation>
<dc:rights xml:lang="pl"><![CDATA[Biblioteka Uniwersytetu Zielonogórskiego]]></dc:rights>
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