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The classical methods for the design of asynchronous state machines are usually complicated due to critical races and hazards, and necessitate special state assignment techniques and hazard free combinational logic leading to extra hardware. The necessity for such special considerations prevents asynchronous designs to take advantage of the CAD tools developed for synchronous machines. ; The contribution of this paper is a novel approach to such designs which enables asynchronous state machines to be systematically synthesized with minimum state variables and arbitrary state encoding. Multiple input changes are allowed. The method uses a separate data driven clock per state variable. The combinational logic is hazard free by default allowing flexibility of minimization. Mealy and Moore outputs can be generated without hazards. ; Simple latches in master-slave configuration are used as memory elements rendering the method suitable for implementation in SSI or VLSI. It avoids extra delay elements often necessary in self-clocked circuits. The simplicity of this method enables the design equations to be derived direct from the Algorithmic State Machines rather than flow tables. The method is illustrated by its application to the design of a VMEbus requester. The methodology is then extended to parallel controllers represented by Petri nets and automated using state assignment techniques already developed for synchronous parallel controllers.