TY - GEN
A1 - Caban, Dariusz
A2 - Caban, Dariusz - red.
PB - Zielona Góra: Uniwersytet Zielonogórski
N2 - Logic verification is based on the comparison of a circuit behavioural specification with its structural realisation. It plays an important part in VLSI design. The circuit descriptions are expressed in a hardware description language. A modified language may simplify the verification process, e.g. the NODEN HDL.
N2 - Logic verification is based on the transformation of different levels of circuit description. to a common, canonical form. Binary Decision Diagrams (BDD) are used for this purpose because of their capability to produce simple models for the results of arithmetic addition. Logic verification is a numerically complex task, which limits its usefulness. Parallel processing on a multi-transputer system can make it more attractive. It is proposed to introduce the parallel processing at the level of constructing the decision diagrams (BDD Engine).
L1 - http://www.zbc.uz.zgora.pl/Content/57283/AMCS_1993_3_1_22.pdf
L2 - http://www.zbc.uz.zgora.pl/Content/57283
KW - sterowanie
KW - sterowanie-teoria
KW - sztuczna inteligencja
KW - matematyka stosowana
KW - informatyka
T1 - A BDD engine for logic verification
UR - http://www.zbc.uz.zgora.pl/dlibra/docmetadata?id=57283
ER -