Improving the LUT count for Mealy FSMs with transformation of output collections - Barkalov, Alexander; Titarenko, Larysa; Mazurkiewicz, Małgorzata (Zielona Góra: Uniwersytet Zielonogórski)
A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments were conducted using standard benchmarks.
Keywords: mealy FSM; FPGA; LUT; synthesis; state codes