A BDD engine for logic verification - Caban, Dariusz (Zielona Góra: Uniwersytet Zielonogórski)
Logic verification is based on the comparison of a circuit behavioural specification with its structural realisation. It plays an important part in VLSI design. The circuit descriptions are expressed in a hardware description language. A modified language may simplify the verification process, e.g. the NODEN HDL.
Keywords: sterowanie; sterowanie-teoria; sztuczna inteligencja; matematyka stosowana; informatyka