Wykorzystanie hierarchicznego modelu współbieżnego automatu w projektowaniu sterowników cyfrowych - Łabiak, Grzegorz (Zielona Góra: Oficyna Uniwersytetu Zielonogórskiego)
The main goal of the thesis is to develop a new modelling method at the system level, which can be applied to designing digital binary controllers whose behaviour may be specified with the statechart diagrams. Next, the controllers are directly implemented in programmable logic devices. Statechart diagrams are considered hierarchical concurrent finite state machines. In the proposed method, the functioning of a control system described with statecharts is translated into an equivalent model in VHDL language, which operates on registers and transfers between them, according to unique new encoding scheme . VHDL model can be an input to commercial software which realises synthesis and implementation in FPGA devices. In distinction from the commercial solution, which transforms statechart diagrams into behavioural model of VHDL language, author's proposition yields better to formal analysis. This advantage allows sophisticated optimization and model checking algorithms can easily be implemented. In the dissertation the algorithm that generates reachability graph is used as an introductory example. In this case, the symbolic state space is represented with the characteristic function and ROBDD.
Keywords: sieci Petriego; binarne diagramy decyzyjne; układy programowalne; układy FPGA; język UML; układy cyfrowe; modelowanie; systemy reaktywne; język SpecCharts; programowa maszyna stanów; notacja graficzna; diagramy statechart; stany proste; stany złożone; zdarzenia; tranzycje proste; tranzycje złożone; atrybut historii; stany synchronizujące; determinizm; system Cosma; systemy CAD; HiCoS; język SSF; rozprawa doktorska; nauki techniczne; informatyka; informatyka (KBN); podstawy teoretyczne informatyki (PKT)