@misc{Czarnecki_Radosław_Kosynteza, author={Czarnecki, Radosław}, howpublished={online}, abstract={In this work the co-synthesis method (COSEDYRES), that optimizes dynamically reconfigurable multiprocessor SOPC system architectures, is presented. The algorithm maximizes speed of a SOPC system, taking into consideration the space constraints of the FPGA. The method is dedicated to the most popular partial reconfigurable FPGAs. The algorithm starts with the initial solution, where all tasks are assigned to only one general purpose processor module. Next, it produces new solutions using iterative improvement methods. Dynamic reconfiguration enables different functionalities to be allocated in the same part of an FPGA.}, abstract={Due to implementation of more tasks in hardware, the overall performance is significantly higher. It is the first co-synthesis algorithm for multiprocessor SOPCs dealing with dynamically self-reconfigurable systems, and one of the first algorithms taking into consideration placement constraints for most popular modern FPGAs. This is also the first co-synthesis algorithm for dynamically reconfigurable SOPC systems that considers mutually exclusive tasks specified by the conditional task graph. In this way, the area occupied by an embedded system can be decreased and free space may be used for other purposes. It was shown that the presented approach can also increase the performance of a SOPC system.}, title={Kosynteza dynamicznie samorekonfigurowalnych systemów wbudowanych}, type={rozprawa doktorska}, keywords={kosynteza, systemy wbudowane, dynamiczna rekonfiguracja, FPGA, warunkowy graf zadań, wbudowane systemy wieloprocesorowe}, }