TY - GEN A1 - Łabiak, Grzegorz PB - Zielona Góra: Oficyna Uniwersytetu Zielonogórskiego N2 - The main goal of the thesis is to develop a new modelling method at the system level, which can be applied to designing digital binary controllers whose behaviour may be specified with the statechart diagrams. Next, the controllers are directly implemented in programmable logic devices. Statechart diagrams are considered hierarchical concurrent finite state machines. In the proposed method, the functioning of a control system described with statecharts is translated into an equivalent model in VHDL language, which operates on registers and transfers between them, according to unique new encoding scheme . VHDL model can be an input to commercial software which realises synthesis and implementation in FPGA devices. In distinction from the commercial solution, which transforms statechart diagrams into behavioural model of VHDL language, author's proposition yields better to formal analysis. This advantage allows sophisticated optimization and model checking algorithms can easily be implemented. In the dissertation the algorithm that generates reachability graph is used as an introductory example. In this case, the symbolic state space is represented with the characteristic function and ROBDD. L1 - http://www.zbc.uz.zgora.pl/Content/500/HTML/Labiak-00.pdf L2 - http://www.zbc.uz.zgora.pl/Content/500 KW - sieci Petriego KW - binarne diagramy decyzyjne KW - układy programowalne KW - układy FPGA KW - język UML KW - układy cyfrowe KW - modelowanie KW - systemy reaktywne KW - język SpecCharts KW - programowa maszyna stanów KW - notacja graficzna KW - diagramy statechart KW - stany proste KW - stany złożone KW - zdarzenia KW - tranzycje proste KW - tranzycje złożone KW - atrybut historii KW - stany synchronizujące KW - determinizm KW - system Cosma KW - systemy CAD KW - HiCoS KW - język SSF KW - rozprawa doktorska KW - nauki techniczne KW - informatyka KW - informatyka (KBN) KW - podstawy teoretyczne informatyki (PKT) T1 - Wykorzystanie hierarchicznego modelu współbieżnego automatu w projektowaniu sterowników cyfrowych UR - http://www.zbc.uz.zgora.pl/dlibra/docmetadata?id=500 ER -